Voltage-controlled oscillators (VCOs) may be used in many applications where a stable, high frequency signal is required. For example, a VCO may be used as part of a phase-locked loop in a frequency synthesizer to provide a plurality of discrete, high resolution clock signals at high frequencies (e.g., in the 10 Mhz-110 Mhz range). In a typical application, these signals may be applied to the clock inputs of integrated circuit (IC) chips in a particular system to synchronize their operations.
FIG. 1 illustrates a typical IC VCO core circuit, which may use pseudo-NMOS NOR gates configured as latches to develop an output signal Vco. The frequency of the output signal Vco from VCO core circuit 10 may be determined by the magnitude of the input drive current I.sub.core. However, a significant problem in manufacturing integrated circuit VCOs using NMOS gates, for example, is that the frequency ranges of the VCO circuits are highly process-dependent. In other words, the "strength" of the NMOS process used to fabricate each VCO IC significantly affects the frequency range of the device.
For example, if the NMOS process used to fabricate the n-channel gates in VCO core circuit 10 was relatively "weak", less n-channel current, I.sub.NCH, will flow in the core. Consequently, signal propagation time through the gates of VCO 10 will be increased, thus decreasing the overall speed of the device. Conversely, if the NMOS fabrication process for VCO circuit 10 was relatively "strong", then the propagation time through the NOR gates would be decreased, thus increasing the speed of the device. FIG. 2 illustrates the frequency variations between typical VCO integrated circuits due to variations in the "strengths" of their respective fabrication processes. Generally, the fabrication processes for these integrated circuits and, therefore, the "strengths" of their n-channel structures, vary from wafer lot to wafer lot.
Generally, to compensate for process variations such as those illustrated by FIG. 2, VCO IC designers may increase the gain (to increase I.sub.core) of individual VCO circuits for relatively "weak" n-channel devices, or decrease the gain (to decrease I.sub.core) of "strong" individual VCOs. Nevertheless, in order to provide a wide range of frequencies with a "weak" VCO, the VCO's gain must be made large enough for the device to produce the highest frequencies in the range, which typically creates a significant design problem in applications that use such a VCO.
FIG. 3 is a block diagram illustrating a phase-locked loop (PLL) circuit including VCO core circuit 10 shown in FIG. 1. PLL circuit 100 may represent a typical design. If the n-channel structure of VCO core circuit 10 is very "weak", then the minimum gain required for VCO core circuit 10 to provide the highest frequencies in a desired range may be relatively high, which will result in a related problem whereby excessive "jitter" may be created at the output of the PLL circuit.
In designing phase-locked loops with a typical VCO, such as core circuit 10, another problem typically arises. In order to counteract open loop gain changes caused by changes in the value of the loop divider, M, the VCO's gain may be controlled by the loop divider, M, as shown in FIG. 3, so as to track those changes. However, as illustrated by FIG. 4, the slope of each gain curve for a respective value of M is controlled from the lowest end-point of the curve (starting at V.sub.VCO). Consequently, the frequency range for the lower values of VCO control voltage (e.g., V.sub.1) is very limited for changes in M, in comparison with the higher control voltages ( e.g., V.sub.2).